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Blog Breaking the Terabit Barrier!

By July 11, 2017No Comments

By: Ed Warnicke, Technical Steering Committee Chair

Since its launch in February of last year, has been delivering complex routing/switching at the multi-million FIB scale at higher performance than any other software vswitch/vrouter. This is  analogous to a shift from something that needs to be delivered via truck (say, an early version of a “computer”) that can now be transferred via carry-on bag (today’s thin and lightweight laptops).

 At launch,’s VPP technology could route/switch at half a Terabit per second at multimillion fib entry scales.  Close examination of the bottlenecks revealed that it was being limited by the ability of the PCI bus to deliver packets from the NIC to the CPU.  VPP had headroom to do more, but the PCI bus bandwidth imposed limitations.

Today we are delighted to announce that limitation has moved further out. The increased PCI bandwidth in the Intel® Xeon® Processor Scalable family have doubled the amount of traffic the PCI bus can deliver to the CPU, and VPP has risen to the occasion without the need of new software optimizations.  This proves what we have long suspected: VPP can route/switch in software at multi-million fib entry scale as much traffic as the PCI bus can throw at it.

When performing at this level, every CPU cycle counts.  The community literally counts the CPU cycles per packet, at a fine granularity within VPP in order to optimize its performance.  The Intel® Xeon® Processor Scalable family also improves VPPs efficiency measured as CPU cycles per packet from 180 to 158 without the need for any new software optimization in VPP.

Many more details can be found in the latest whitepaper, the official press release, and the video below.